1. Field of the Invention
This invention relates to phase-locked loops (PLLs).
2. Description of the Related Art
FIG. 1 illustrates a prior art analog fractional-N PLL where the VCOCLK 101 is a non-integer multiple of the reference clock (RefCLK) 103. The fractional-N divider 107 supplies a feedback signal (divout) 108 to a phase and frequency detector (PFD) and charge pump 110 that determines the time difference between edges of the RefCLK signal 103 and the feedback signal 108 and supplies a phase error signal based on the time difference to the loop filter 119. The divide value 105, which is supplied to the fractional-N divider 107, is modulated in time to achieve an average divide value corresponding to the desired divide value 109 supplied to the delta sigma modulator logic 111, which introduces quantization noise. The delta sigma (Δ−Σ) modulator logic 111 supplies a digital error signal 115 based on the difference between the divide value 105 supplied to the fractional-N divider and the desired divide value 109. The illustrated prior art PLL includes a digital-to-analog converter (DAC) 117 having a current-based output to convert the digital error signal 115 to a current that is added to the charge pump output signal and supplied to the loop filter 119 to reduce quantization noise. Other prior art approaches to reduce quanitzatin noise utilize digital cancellation of the quantization noise in the case of digital PLLs. For the analog PLL case, the use of the current DAC leads to increased power and area when striving for low noise. For the digital PLL case, the use of all digital cancellation relies on having a high performance Time-to-Digital Converter (TDC) that has adequately high resolution and linearity to achieve a desired level of phase noise performance. The implementation of such a TDC can be quite challenging when excellent noise performance is desired of the PLL. Accordingly, improvements in quantization noise cancellation are desirable.
However, even where quantization noise is successfully canceled, signals generated by phase-locked loops can include undesirable spurious tones. Cancellation of such tones is desirable along with improvements in cancellation techniques.
While FIG. 1 shows an analog PLL, digitally controlled oscillators have become common in PLLs. There is a need to achieve high resolution conversion of the phase error between the feedback clock and the reference clock to a digital value. Accordingly, improvements in generating a digital representation of the phase error is desirable.